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Quad SPI-3 to SPI-4 Link Layer
Lattice Semiconductor
Signal Descriptions
Table 4. Signal De?nitions for Quad SPI-3 to SPI-4 Link Bridge Solution I/O
Bridge Core User’s Guide
Signal Name
SPI-3 Signals 1
RFCLK
TFCLK
RERR
RENB
RVAL
RDAT [31:0]
RMOD [1:0]
RPRTY
RSX
RSOP
REOP
TSX
TENB
TERR
TSOP
TEOP
TDAT [31:0]
TMOD [1:0]
TPRTY
TADR [2:0]
DTPA [7:0]
STPA
PTPA
SPI-4 Signals 2
ARDAT[15:0]P
ARDAT[15:0]N
ARCTLP
ARCTLN
ARDCLKP
ARDCLKN
ARSTAT[1:0]P
ARSTAT[1:0]N
ARSCLKP
ARSCLKN
RSTAT[1:0]A
RSCLKA
ATDAT[15:0]P
ATDAT[15:0]N
ATCTLP
ATCTLN
Direction
Input
Input
Input
Output
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Description
SPI-3 Interface Clock
SPI-3 Interface Clock (from Transmit FIFO)
Receive Error Indicator
Receive Read Enable
Receive Data Valid
Receive Packet Data Bus
Receive Word Modulo
Receive Bus Parity
Receive Start of Transfer
Receive Start of Packet
Receive End of Packet
Transmit Start of Transfer
Transmit Write Enable
Transmit Error Indicator
Transmit Start of Packet
Transmit End of Packet
Transmit Packet Data Bus
Transmit Word Modulo
Transmit Bus Parity
Transmit PHY Address Bus
Direct Transmit Packet Available
Selected PHY Transmit Packet Available
Polled PHY Transmit Packet Available
LVDS signals for SPI-4.2 RXA
LVDS signal for RXA Control
Differential RXA Data clock signal
LVDS Status Output
LVDS Status Output Clock
LVTTL Status Output
LVTTL Status Clock Output
LVDS signals for SPI-4.2 TXA
Transmit Control for SpiSPI-4.2 TXA
10
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